1. Field of the Invention
The present invention relates to a fabrication process for a semiconductor substrate and, more particularly, to a process for fabricating a single-crystal semiconductor on a dielectric isolation or an insulator and a single-crystal compound semiconductor on Si substrate and further to a process for fabricating a semiconductor substrate suitable for electronic devices and integrated circuits made in a single-crystal semiconductor layer.
2. Related Background Art
Formation of a single-crystal Si semiconductor layer on an insulator is widely known as Si On Insulator (SOI) technology and much research has been focused thereon, because devices obtained utilizing the SOI technology have many advantages that cannot be achieved by the normal bulk Si substrates for fabrication of Si integrated circuits. Namely, use of SOI technology can enjoy the following advantages, for example:
1. Dielectric isolation is easy and high integration is possible.
2. Radiation resistance is high.
3. Stray capacitance is reduced and the operation speed can be enhanced.
4. The well process can be omitted.
5. Latch-up can be prevented.
6. Fully depleted field effect transistors can be fabricated by thin-film structure. These advantages are described in further detail, for example, in the reference [Special Issue: "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, no 3, pp 429-590 (1983)].
In recent years, many reports have been presented on the SOI as a substrate focused on increase of speed and decrease of consumption power of MOSFET (IEEE SOI conference 1994). Since the SOI structure has an insulating layer below the device, use thereof can simplify the device isolation process as compared with forming the devices on a bulk Si wafer, which results in shortening the device process steps. Namely, in addition to the increase in performance, the total costs including the wafer cost and the process cost are expected to be lower than those of MOSFETs and ICs on bulk Si.
Among others, the fully depleted MOSFETs are expected to increase the speed and decrease the consumption power due to an improvement in driving force. The threshold voltage (Vth) of MOSFET is determined in general by an impurity concentration of the channel portion, and, in the case of the fully depleted (FD) MOSFETs using the SOI, the thickness of a depletion layer is also influenced by the film thickness of the SOI. Accordingly, evenness of the film thickness of SOI is highly desirable for fabricating large-scale integrated circuits with good yields.
On the other hand, the devices on a compound semiconductor have high performance that cannot be attained by Si, for example, high-speed operation, radiation of light, and so on. Presently, most of these devices are fabricated in a layer epitaxially grown on a compound semiconductor substrate of GaAs or the like. The compound semiconductor substrates, however, have problems such as high expensive, low mechanical strength, difficulty in fabricating a large-area wafer, etc.
Because of these problems, attempts have been made to hetero-epitaxially grow a compound semiconductor on the Si wafer, which is cheap, has high mechanical strength, and permits fabrication of a large-area wafer.
Returning to the SOI structure, research on formation of SOI substrates has been active since the 1970s. In the early stage, much research was focused on a method for hetero-epitaxially growing single-crystal Si on a sapphire substrate as an insulator (SOS: Silicon on Sapphire), a method for forming the SOI structure by dielectric isolation based on oxidation of porous Si (FIPOS: Full Isolation by Porous Oxidized Silicon), and an oxygen ion implantation method.
The FIPOS method is a method for forming an n-type Si layer in an island pattern on a surface of a p-type Si single-crystal substrate by proton implantation (Imai et al., J. Crystal Growth, vol 63, 547 (1983)) or by epitaxial growth and patterning, making only the p-type Si substrate porous from the surface, so as to surround Si islands by anodization in HF solution, and then dielectric-isolating the n-type Si islands by enhanced oxidation. This method has a problem in that degrees of freedom on device designing are limited, because the Si regions isolated are determined prior to the device processes.
The oxygen ion implantation method is called SIMOX, which was first reported by K. Izumi. Oxygen ions are first implanted in about 10.sup.17 to 10.sup.18 /cm.sup.2 into Si wafer, and thereafter the wafer is annealed at a high temperature of approximately 1320.degree. C. in an argon-oxygen atmosphere. As a result, the oxygen ions implanted around the depth corresponding to the projected range (Rp) of ion implantation are bound with Si to form an oxidized Si layer. At that point, a Si layer, amorphized by the oxygen ion implantation above the oxidized Si layer, is also recrystallized to form a single-crystal Si layer. Crystalline defects in the surface Si layer were as many as 10.sup.5 /cm.sup.2 before, but they were successfully decreased to below 10.sup.2 /cm.sup.2 by adjusting the amount of implantation of oxygen to approximately 4.times.10.sup.17 /cm.sup.2. However, the film thicknesses of the surface Si layer and the buried, oxidized Si layer (BOX; Buried Oxide) were limited to specific values due to narrow ranges of implantation energy and implantation dose capable of maintaining the film quality of the oxidized Si layer, crystallinity of the surface Si layer, and so on. Sacrificial oxidation or epitaxial growth was necessary for obtaining the surface Si layer in a desired film thickness. In that case, there is a problem that evenness of film thickness is degraded, because degradation due to these processes is added on the distribution of film thickness.
It is also reported that malformed regions of oxidized Si called pipes exist in the BOX. One of causes thereof is conceivably contaminations such as dust upon implantation. In the portions including the pipes, degradation of device characteristics occurs due to leakage between the active layer and the support substrate.
Since the implantation dose in the ion implantation of SIMOX is larger than in the ion implantation used for the normal semiconductor processes as described previously, the implantation time is still long even after dedicated equipment has been developed. Since the ion implantation is carried out by raster scan of an ion beam of a predetermined electric current amount or by expanding the beam, an increase in the implantation time is anticipated with an increase in the area of wafer. In high-temperature annealing of a large-area wafer, it is pointed out that the problem of generation of slip or the like due to the temperature distribution within the wafer becomes more severe. Annealing at high temperatures, such as 1320.degree. C., which are not used normally in the Si semiconductor processes, is indispensable for the SIMOX, and there is thus such a concern that the above problem becomes more significant, including development of equipment.
Aside from the conventional SOI forming methods described above, attention has recently focused on another method for bonding Si single-crystal substrate to another Si single-crystal substrate thermally oxidized, by annealing or with an adhesive, thereby forming the SOI structure. This method requires evenly thinning the active layer for the device. In other words, it is necessary to thin the Si single-crystal substrate even several hundred .mu.m thick down to the order of .mu.m or less. The following three types of methods are available for this thinning:
(1) thinning by polishing PA1 (2) thinning by localized plasma etching PA1 (3) thinning by selective etching.
It is difficult to achieve uniform thinning by the polishing method of (1). In particular, several ten % of dispersion appears in thinning on the sub-.mu.m order, and evening of this dispersion is a big problem. The degree of difficulty increases with further increases in the diameter of a given wafer.
The above method of (2) is used to thin the layer roughly by the method of polishing of (1) to about 1 to 3 .mu.m and to measure a distribution of film thicknesses at multiple points over the entire surface. After that, based on this distribution of film thicknesses, the layer is etched to correct the distribution of film thicknesses by scanning it with a plasma using SF.sub.6 or the like in the diameter of several mm, whereby the layer is thinned down to a desired film thickness. It is reported that this method can achieve the film thickness distribution of about .+-.10 nm. However, if there are contaminants (particles) on the substrate upon plasma etching, the contaminants will serve as an etching mask, thereby forming projections on the substrate.
Since the surface is rough immediately after etching, touch polishing is necessary after completion of the plasma etching. Control of the amount of polishing is carried out by time management, and thus control of degradation of the final film thickness and of the film thickness distribution by polishing is possible. Further, because in polishing, an abrasive such as colloidal silica directly rubs the surface to become the active layer, concerns exist about formation of a crush layer and introduction of work strain by polishing. As the wafers further increase in area, the time for plasma etching also increases proportionally which also raises another concern about an extreme drop of throughput.
The above method of (3) is a method for preliminarily forming a selectively etchable film structure in a substrate to be thinned. For example, a thin layer of p.sup.+ -Si containing boron in a concentration of 10.sup.19 or more/cm.sup.3 and a thin layer of p-type Si are stacked on a p-type substrate by the method of epitaxial growth or the like, thereby obtaining a first substrate. This is bonded to a second substrate through an insulating layer of oxide film or the like and thereafter the back face of the first substrate is preliminarily thinned by grinding and polishing. After that, the p.sup.+ -layer is exposed by selective etching of the p-type substrate and the p-type thin layer is exposed by selective etching of the p.sup.+ -layer, thus completing the SOI structure. This method is described in detail in the report of Maszara (J. Electrochem. Soc. 138, 341 (1991)).
Although the selective etching is said to be effective for uniform thinning, it has the following problems:
The etch selectivity is not sufficient, at most 10.sup.2.
It requires touch polishing after etching, because the surface flatness after etching is poor. This, however, results in a decrease in the film thickness and a tendency to degrade the uniformity of film thickness. Polish amounts are managed by polishing time polishing, but rates vary greatly, which makes controlling the amount of polish difficult. Accordingly, a problem arises particularly in forming a very thin SOI layer, for example, 100 nm thick.
Crystallinity of the SOI layer is poor due to use of ion implantation and epitaxial growth or hetero-epitaxial growth on the high-concentration-B-doped Si layer. The surface flatness of the bonded surfaces are inferior to normal Si wafers.
Thus, the method of (3) has the above problems (C. Harendt, et al., J. Elect. Mater. Vol. 20, 267 (1991), H. Baumgart, et al., Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp-733 (1991); C. E. Hunt, Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp-696 (1991)). Also, the selectivity of selective etching is greatly dependent on concentration differences of impurities of boron or the like and steepness of its depthwise profile. Therefore, if high-temperature bonding annealing is conducted in order to enhance the bonding strength, or if high-temperature epitaxial growth is conducted in order to improve crystallinity, the depthwise distribution of impurity concentration will expand to degrade the etch selectivity. This illustrates the difficulty in realizing both an improvement in etch selectivity and an improvement in bonding strength.
Recently, Yonehara et al., solving such problems, reported the bonding SOI excellent in uniformity of film thickness and in crystallinity and capable of being batch-processed (T. Yonehara, K. Sakaguchi and N. Sato, Appl. Phys. Lett. 64, 2108 (1994)). This method uses a porous layer 42 on an Si substrate 41, as a material of selective etching. A non-porous single-crystal Si layer 43 is epitaxially grown on the porous layer and thereafter it is bonded to a second substrate 44 through an oxidized Si layer 45 (FIG. 14). The first substrate is thinned from its back surface by a method of grinding or the like, to expose the porous Si 42 across the entire surface of substrate (FIG. 15). The porous Si 42 thus exposed is removed by etching with a selective etchant such as KOH or HF+H.sub.2 O.sub.2 (FIG. 16). At this time, the etch selectivity of porous Si to bulk Si (non-porous single-crystal Si) is sufficiently high, about 100,000. Hence, the non-porous single-crystal Si layer preliminarily grown on the porous layer can be left on the second substrate with little reduction of film thickness thereof, thus forming the SOI substrate. Therefore, the uniformity of film thickness of SOI is determined almost upon epitaxial growth. Since the epitaxial growth allows use of the CVD system used in the normal semiconductor processes, it realized the uniformity thereof, for example 100 nm.+-.within 2%, according to the report of Sato et al. (SSDM 95). Also, the crystallinity of the epitaxial Si layer was reported to be as good as 3.5.times.10.sup.2 /cm.sup.2.
Since in the conventional methods the etch selectivity depended on the differences of impurity concentration and the depthwise profile, temperatures of thermal treatments (bonding, epitaxial growth, oxidation, etc.) to expand the concentration distribution were greatly restricted to below approximately 800.degree. C. On the other hand, in the etching of this method, the etch rate is determined by the difference of structure between porous and bulk, and thus there is little restriction on the temperature of the thermal treatments. It is reported that thermal treatment at about 1180.degree. C. is possible. For example, annealing after bonding is known to enhance the bonding strength between wafers and to decrease the number and size of vacancies (voids) occurring in the bonding interface. In such etching based on the structural difference, particles deposited on porous Si at the etching process, if present, do not affect the uniformity of film thickness.
However, the semiconductor substrate using bonding always requires two wafers, most of one of which is wastefully removed and discarded by polishing, etching, etc., which would result in wasting the earth's limited resources.
Accordingly, SOI by bonding, according to the existing methods, has a lot of problems in the regarding controllability, uniformity, and cost efficiency.
Recently, Sakaguchi et al. reported a method for reusing the first substrate, which was consumed in the above bonding method (Japanese Patent Application No. 07-045441 (1995)).
They employed the following method in place of the step of thinning the first substrate from the back surface by the method of grinding, etching, and the like to expose porous Si in the bonding plus etchback process using porous Si as described above.
A surface layer of a first Si substrate 51 is made porous to obtain a porous layer 52, a single-crystal Si layer 53 is formed thereon, and this single-crystal Si layer 53 and first Si substrate is bonded through an insulating layer 55 with a principal surface of second Si substrate 54 (FIG. 17). After this, the bonding wafer is divided at the porous layer (FIG. 18), and the porous Si layer exposed in the surface on the second Si substrate side is selectively removed, thereby forming an SOI substrate (FIG. 19).
Division of the bonding wafer is effected by using a method for breaking the porous Si layer, for example, a method for applying sufficient tension or pressure perpendicularly to and uniformly in the surface of the bonding wafer, a method for applying wave energy of ultrasonic wave or the like, a method for exposing the porous layer on the side face of wafer, etching some of the porous layer, and inserting an edge of a razor into the porous layer, a method for exposing the porous layer on the side face of wafer, infiltrating a liquid such as water into the porous Si layer, and thereafter expanding the liquid by heating or cooling the entire bonding wafer, a method for applying force horizontally onto the second (or first) substrate relative to the first (or second) substrate, or the like.
These methods are all based on the idea that the mechanical strength of porous Si, depending upon its porosity, is sufficiently less than that of bulk Si. For example, with a porosity of 50%, the mechanical strength of porous Si may be considered to be half that of bulk Si. Namely, when compression, tension or shear force is exerted on the bonding wafer, the porous Si layer is broken first. With a greater porosity, the porous layer can be broken by a weaker force.
However, when force is exerted vertically or horizontally on the surface of wafer, the wafer is sometimes elastically deformed, thereby failing to properly exert force on the porous layer. This is observed because the semiconductor substrate is not a perfectly rigid body, but rather is an elastic body and this also depends on the method of supporting a given wafer.
Similarly, with the method for inserting an edge of a razor or the like through the side surface of wafer, the yields were extremely lowered in some cases where the thickness of the razor was not sufficiently thin or where the razor did not have sufficiently high rigidity.
Also, the razor was not able to be inserted uniformly from the periphery or the force was exerted from the outside on the bonding wafer. As a result, if the bond strength of the bonding surface was weaker than the strength of the porous Si layer or if there existed a locally weak portion, the two wafers were split at the bonding surface, thereby sometimes failing to achieve the initial purpose.
Accordingly, a desire exists for a method for fabricating SOI substrates of sufficient quality with good reproducibility and, at the same time, realizing conservation of resources and reduction of cost by re-use of a wafer or the like.
The bulletin of Japanese Laid-open Patent Application No. 5-211128 (1993) describes a proposal for a method for forming a bubble layer by ion implantation, annealing it to cause rearrangement of crystal and cohesion of bubbles, and dividing the wafer through the bubble layer, wherein optimization of annealing is not easy and is carried out at low temperatures of 400 to 600.degree. C. Annealing at such low temperatures cannot suppress generation of voids as described above, and the voids once generated cannot be nullified even with re-annealing at high temperature after thinning. Namely, the decrease in the number and size of voids is a phenomenon that occurs when the two wafers are annealed at high temperature in the bonded state, and high-temperature annealing after thinning will increase the strength of the adhesive portion, but will not decrease the voids.
The above description concerns the problems related to the SOI technology by bonding. There are also demands as to the SOI technology regarding formation of a single-crystal layer on a light transparent substrate, formation of a compound semiconductor layer on a substrate, and so on, for the following reasons:
The light transparent substrate is important in constructing contact sensors which serve as light receiving elements, and projection type liquid crystal image display devices. Further, high-performance drive elements are necessary for realizing higher-density, higher-resolution, and higher-definition of pixels (picture elements) in the sensors and display devices. As a result, the devices provided on the light transparent substrate need to be fabricated using a single-crystal layer having excellent crystallinity. Use of the single-crystal layer enables peripheral circuits for driving the pixels and circuits for image processing to be incorporated in the same substrate as the pixels, thereby realizing size reduction and speed enhancement of a given chip.
However, the light transparent substrate typified by glass has disorderliness as to its crystal structure in general, and a thin Si layer deposited thereon is an amorphous layer or, at best, a polycrystal layer, reflecting the disorderliness of the substrate. High-performance devices cannot be fabricated of such a substrate. Namely, because of a crystal structure with many imperfections, it is not easy to fabricate drive elements of amorphous and polycrystal Si having sufficient performance that is required now or in the future. It is because the crystal structure of the substrate is amorphous, and simple deposition of Si layer will not yield a single-crystal layer with good quality.
On the other hand, substrates of compound semiconductor are necessary and indispensable for fabricating devices of compound semiconductor, but the substrates of compound semiconductor are expensive and it is very difficult to form a large area of compound semiconductor. For these reasons, attempts have been made to hetero-epitaxially grow a compound semiconductor of GaAs or the like on the Si wafer, which can be fabricated as a large-area wafer.
However, the thus grown film has poor crystallinity because of differences of lattice constant and coefficient of thermal expansion and it is thus very difficult to apply it to devices.
It is, therefore, an object of the present invention to provide a process for fabricating a film with good crystallinity and to provide a process for fabricating a semiconductor substrate, which can effectively use the semiconductor substrate as a material and which can suitably achieve conservation of resources and reduction of cost.